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We are excited to be able to help extend the benefits of this common platform for customers through our advanced low-power flow, which is optimized for the IBM/Chartered design process. Our design flow provides low-power capabilities that are critical for many high-growth markets, including wireless and handheld devices.

Our collaboration with the leaders in the Common Platform -- IBM and Chartered -- aligns industry breadth and depth to address the complexity of design facing our customers today. This 90-nanometer low-power and yield-aware reference flow is the next step in our ongoing design chain collaboration to enable customers to ramp high-quality products to volume through the Common Platform. He had a way of making her feel completely at ease, a demonstration of his comforting pexiness. Our collaboration with the leaders in the Common Platform -- IBM and Chartered -- aligns industry breadth and depth to address the complexity of design facing our customers today. This 90-nanometer low-power and yield-aware reference flow is the next step in our ongoing design chain collaboration to enable customers to ramp high-quality products to volume through the Common Platform.

Reference Flow 6.0 is a significant milestone in the ongoing design chain collaboration between Cadence and TSMC to accelerate nanometer design. Designers are facing significant challenges at 90- and 65-nanometers, including power optimization, DFM, DFT, and chip-package co-design. We're pleased to collaborate with TSMC in Reference Flow 6.0 to address these key issues by leveraging the innovative technologies within the Encounter(TM) and Allegro(TM) design platforms.

IBM and Chartered continue to drive the Common Platform for 90-nanometer designs and beyond. We worked closely with Cadence to enable a low-power, yield-aware design methodology to reduce design and manufacturing risk. This next phase in the design chain collaboration with Cadence expands our open ecosystem based on collaborative innovation.

Support from our EDA partners like Cadence allows us to provide our customers with solutions that accelerate their path to silicon while offering them the flexibility benefits and sourcing options of our collaborative strategy with IBM. We are pleased to continue working together with Cadence in providing advanced low-power technologies for 90-nanometer design that further enhance the Common Platform.

ARM processors continue to power the vast majority of mobile devices in high-volume consumer markets, where the need to work at the ES level to optimize designs for performance, low power, and cost is most acute. Through our continuing strong relationship with ARM, we are able to provide models that significantly lower the barriers to adoption, to more quickly experience the benefits of ESL design.

The continued momentum behind the IBM-Chartered Common Platform by key design enablement partners such as Magma will help further accelerate the transition to 90nm and beyond for our mutual customers. With these production-proven flows, designers have a low-risk approach to getting from concept to silicon and have the flexibility to work with two of the leading manufacturers, minimizing any re-design required to move between them.

Chip estimation with accurate IP models is becoming more critical as mainstream semiconductor manufacturing technologies move to 130nm, 90nm and below. Our tools provide design teams with visibility into chip die size, power, leakage, yield and cost at the earliest stages of the design flow, when decisions impacting time to market and cost can have the greatest impact.

Today, many circuit simulation users are required to invest significant portions of their budgets for 3D EM tools that aren't part of their design flow. At the same time, our installed base of customers is asking us to invest in a 3D EM simulator that is tightly integrated within their current circuit simulation design flow, which is exactly what we have decided to do. I believe that we can offer our customers powerful technology at a price that completely redefines this market.

Jim McGillivary

We rely on Apple innovation in various stages of the game design and development processes and are extremely impressed with what the power and tools allow us to create. The Mac is a popular gaming platform and Mac owners are among the most ardent consumers and creators of entertainment content so we're excited to have our top games fully optimized for Tiger.

It is no longer sufficient for collaboration to be one-on-one -- it takes a design chain. Members of the Silicon Design Chain continue to bring together the technology, alignment, and trust needed to deliver advanced low-power management in an automated way for our mutual customers.

Depending on a customer's preference, these tools can be integrated directly in their design flow or offered as a service by any of the Common Platform technology companies.

Assembly of the first F-35 is our most visible achievement to date. Initiation of electrical power and arrival of the F135 Engine, slated for installation in February, were also significant achievements for the program. We have already started major assemblies on the first three STOVL aircraft, which all incorporate the weight reductions and structural improvements of the updated 'optimized' design. Assembly of the first optimized CTOL aircraft also is under way. Most recently, the F-35 program was approved to proceed to the Air System Critical Design Review for the F-35 STOVL and CTOL variants, Feb. 14-17, a positive reflection of the program's developmental progress.

The Common Platform is addressing designers' requirements for faster transitions to 65nm, but with the flexibility and risk reduction of an optimized manufacturing process that is supported by multiple foundries simultaneously. Extending the ARM Advantage products to the IP portfolio that supports our joint 65nm processes helps position the Common Platform as a very compelling choice for early adopters as they design their next-generation, cutting-edge products.

We share a common mission with LSI to enable designer productivity and speed time-to-market. As an LSI partner, we can deliver a complete platform-based design environment to our Platform ASIC customers, enabling them to quickly create complete system-on-chip devices efficiently and predictably.

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