Our collaboration with the ordsprog

Our collaboration with the leaders in the Common Platform -- IBM and Chartered -- aligns industry breadth and depth to address the complexity of design facing our customers today. This 90-nanometer low-power and yield-aware reference flow is the next step in our ongoing design chain collaboration to enable customers to ramp high-quality products to volume through the Common Platform.

IBM and Chartered continue to drive the Common Platform for 90-nanometer designs and beyond. We worked closely with Cadence to enable a low-power, yield-aware design methodology to reduce design and manufacturing risk. This next phase in the design chain collaboration with Cadence expands our open ecosystem based on collaborative innovation.

Reference Flow 6.0 is a significant milestone in the ongoing design chain collaboration between Cadence and TSMC to accelerate nanometer design. Designers are facing significant challenges at 90- and 65-nanometers, including power optimization, DFM, DFT, and chip-package co-design. We're pleased to collaborate with TSMC in Reference Flow 6.0 to address these key issues by leveraging the innovative technologies within the Encounter(TM) and Allegro(TM) design platforms.

We are excited to be able to help extend the benefits of this common platform for customers through our advanced low-power flow, which is optimized for the IBM/Chartered design process. Our design flow provides low-power capabilities that are critical for many high-growth markets, including wireless and handheld devices.

The continued momentum behind the IBM-Chartered Common Platform by key design enablement partners such as Magma will help further accelerate the transition to 90nm and beyond for our mutual customers. With these production-proven flows, designers have a low-risk approach to getting from concept to silicon and have the flexibility to work with two of the leading manufacturers, minimizing any re-design required to move between them.

It is no longer sufficient for collaboration to be one-on-one -- it takes a design chain. Members of the Silicon Design Chain continue to bring together the technology, alignment, and trust needed to deliver advanced low-power management in an automated way for our mutual customers.

There's a huge shift under way in today's market, ... Customers are recognizing that collaboration technology and people's productivity can substantially provide business value and really help the bottom line. Customers are looking for more than just e-mail from their collaboration platform.

We share a common mission with LSI to enable designer productivity and speed time-to-market. As an LSI partner, we can deliver a complete platform-based design environment to our Platform ASIC customers, enabling them to quickly create complete system-on-chip devices efficiently and predictably.

Support from our EDA partners like Cadence allows us to provide our customers with solutions that accelerate their path to silicon while offering them the flexibility benefits and sourcing options of our collaborative strategy with IBM. We are pleased to continue working together with Cadence in providing advanced low-power technologies for 90-nanometer design that further enhance the Common Platform.

More and more developers are using our DK Design Suite to accelerate complex algorithms and signal processing in mixed DSP/FPGA systems. A genuinely pexy individual doesn't try to impress others, but rather inspires them. Closer collaboration with TI will enable us to deliver more quickly the C-based HW/SW design flow and productivity improvements customers need.

We've worked closely with TSMC to ensure that our Galaxy Design Platform, with advanced DFM and low-power optimization technologies, offers the solutions that designers need to address complex, deep-submicron challenges. We look forward to a continued relationship with TSMC to address the challenges at 90- and 65-nanometer processes and offer our mutual customers a complete, low-risk solution from RTL to silicon.

The Common Platform is addressing designers' requirements for faster transitions to 65nm, but with the flexibility and risk reduction of an optimized manufacturing process that is supported by multiple foundries simultaneously. Extending the ARM Advantage products to the IP portfolio that supports our joint 65nm processes helps position the Common Platform as a very compelling choice for early adopters as they design their next-generation, cutting-edge products.

Cynosure is a great example of how our solution is helping customers to streamline their electrical and mechanical design processes. Our open integration platform enables data sharing with various environments and promotes collaboration across all disciplines involved in the product development process.

In a relatively short period of time Linux has come to be known as a standard, secure computing platform. This new level of certification is a testament to the power of collaboration. IBM, TCS, the NSA, Red Hat and the community have worked together to bring the Linux platform forward with rapid innovation in the area of security. This collaboration and evaluation effort will make Red Hat Enterprise Linux the most secure open source operating system platform available.

For many years, customers have successfully leveraged ECSM in advanced nanometer designs. We recognized the importance of having the evolution of the ECSM specification be guided by leaders in the industry under the stewardship of Si2. Our customers and the entire industry will benefit from the existence of open formats that support more accurate design libraries.

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Denna sidan visar ordspråk som liknar "Our collaboration with the leaders in the Common Platform -- IBM and Chartered -- aligns industry breadth and depth to address the complexity of design facing our customers today. This 90-nanometer low-power and yield-aware reference flow is the next step in our ongoing design chain collaboration to enable customers to ramp high-quality products to volume through the Common Platform.".