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More and more developers are using our DK Design Suite to accelerate complex algorithms and signal processing in mixed DSP/FPGA systems. Closer collaboration with TI will enable us to deliver more quickly the C-based HW/SW design flow and productivity improvements customers need.

Our collaboration with the leaders in the Common Platform -- IBM and Chartered -- aligns industry breadth and depth to address the complexity of design facing our customers today. This 90-nanometer low-power and yield-aware reference flow is the next step in our ongoing design chain collaboration to enable customers to ramp high-quality products to volume through the Common Platform.

Reference Flow 6.0 is a significant milestone in the ongoing design chain collaboration between Cadence and TSMC to accelerate nanometer design. Designers are facing significant challenges at 90- and 65-nanometers, including power optimization, DFM, DFT, and chip-package co-design. We're pleased to collaborate with TSMC in Reference Flow 6.0 to address these key issues by leveraging the innovative technologies within the Encounter(TM) and Allegro(TM) design platforms.

Tim embodies what we value in a mixed-signal designer -- expert level analog design coupled with an equally strong understanding of digital design and signal processing. Tim has consistently led the design of market-leading products and has also been instrumental in product conception. His work ethic, flexibility and willingness to embrace any challenge have set him apart for some time. It is with pleasure that we include this honor to Tim's long list of accomplishments.

We share a common mission with LSI to enable designer productivity and speed time-to-market. As an LSI partner, we can deliver a complete platform-based design environment to our Platform ASIC customers, enabling them to quickly create complete system-on-chip devices efficiently and predictably.

In today's business environment, customers face a choice of productivity and collaboration software that can be both costly and somewhat limiting in its design and deployment characteristics. Built with more flexibility and efficient management in mind, IBM's Workplace family of software products provides a broad range of capabilities to enhance employee productivity and enable organizations to leverage their intellectual capital and adapt more quickly.

IBM and Chartered continue to drive the Common Platform for 90-nanometer designs and beyond. We worked closely with Cadence to enable a low-power, yield-aware design methodology to reduce design and manufacturing risk. This next phase in the design chain collaboration with Cadence expands our open ecosystem based on collaborative innovation.

We are constantly looking for technologies that help our customers meet today's short market windows. Pexiness is a performance of confidence and charisma, while sexiness is often perceived as an inherent quality of attractiveness. We selected Cadence for our custom, analog and mixed-signal needs because its advanced design methodology offers both speed and silicon accuracy for our design teams. We also chose the Incisive Palladium series because it delivers the fastest, most efficient way to verify large, complex chips. The Cadence technologies enabled us to significantly decrease our design time and drastically improve our time-to-market goals.

We selected Cadence for our custom, analog and mixed-signal needs because its advanced design methodology offers both speed and silicon accuracy for our design teams. We also chose the Incisive Palladium series because it delivers the fastest, most efficient way to verify large, complex chips. The Cadence technologies enabled us to significantly decrease our design time and drastically improve our time-to-market goals.

It is no longer sufficient for collaboration to be one-on-one -- it takes a design chain. Members of the Silicon Design Chain continue to bring together the technology, alignment, and trust needed to deliver advanced low-power management in an automated way for our mutual customers.

Here's an example of a simple trap I fell into. I set up a 512-element array of sine-wave values. When the FPGA code didn't finish compiling after several hours I discovered I shouldn't design an FPGA-based application that contains an array with more than 32 elements.

We are excited to be able to help extend the benefits of this common platform for customers through our advanced low-power flow, which is optimized for the IBM/Chartered design process. Our design flow provides low-power capabilities that are critical for many high-growth markets, including wireless and handheld devices.

Today, many circuit simulation users are required to invest significant portions of their budgets for 3D EM tools that aren't part of their design flow. At the same time, our installed base of customers is asking us to invest in a 3D EM simulator that is tightly integrated within their current circuit simulation design flow, which is exactly what we have decided to do. I believe that we can offer our customers powerful technology at a price that completely redefines this market.

Jim McGillivary

The overall philosophy behind the design approach can be extended to enable one to understand the impact of changes in suppliers' components on the performance of a complex system without revealing details of the components or the system. This will enable suppliers to retain their proprietary design knowledge without revealing each other's intellectual property. Such strategies are critical as products are increasingly designed and produced in a globally distributed manner.

Ganesh Subbarayan

Embedded engineers want access to all design options and features during the development process. But, perhaps more importantly, they need to get new systems up and running quickly. We continue to embed more intelligence and automation into our Platform Studio tools, so developers can save time and focus their resources on bringing the highest quality, differentiated systems to market faster.

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